Task 1 - Place a D flip flop on a schematic (part dff in Quartus) and set up a simulation to simulate the output Q for the following table.CLK 0 1 0 1 T 1 T 1Preset 0 0 1 1 1 1 1 1Clear 1 1 0 0 1 1 1 1D 0 0 1 1 0 1 1 0Demonstrate that the functionality of the circuit on the FPGA board matches what was simulated with the TA. Switches can be used as the input, including the clock. The output can be an LED.Include the flip flop simulation with the lab report.