Nasdaq

Synopsys' Fusion Compiler Adopted by AMD

AMD deploys Synopsys' Fusion Compiler RTL-to-GDSII product for the development of its next-generation processor products Unique, single-data-model architecture and unified, full-flow optimization ...
Electronic Design

Design Compiler Points Toward Better Physical Implementation

Synopsys' Design Compiler 2010 accounts for the challenges of modern physical IC design, offering floor plan exploration from within the synthesis environment. It also delivers physical guidance to IC ...
Design-Reuse

Axell Switches to Synopsys' Design Compiler RTL Synthesis Solution for Graphics IC Designs

MOUNTAIN VIEW, Calif., Dec. 14, 2015 – Synopsys, Inc. (Nasdaq: SNPS) today announced that Axell, a leading fabless design company of graphics chips for interactive entertainment and industrial ...
Design-Reuse

Cadence Expands C-to-Silicon Compiler with High-level Synthesis Support for Altera and ...

Integration Enables High-level Synthesis of Mixed Control/Datapath Designs and Incremental Synthesis for FPGAs SAN JOSE, Calif., and TOKYO, 20 Jan 2009-- Cadence Design Systems, Inc. (NASDAQ: CDNS), ...
Electronic Design

System Compiler Speeds Front-End IC Design

Said to bring fully automated, accurate timing and block information to front-end integrated IC design, the TOPOMO physical system compiler integrates and automates block partitioning, block placement ...