资讯

Semiconductor Engineering

A Primer On Last-Level Cache Memory For SoC Designs

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver ...
Design-Reuse

Using OCP and Coherence Extensions to Support System-Level Cache Coherence

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
Design-Reuse

Adding Cache to IPs and SoCs

• Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. • Technologies like AMBA protocols facilitate cache coherence and efficient data management ...
Semiconductor Engineering

How Memory Design Optimizes System Performance

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
Electronic Design

Server Processors Stack Up to 1.1 GB of 3D Cache

Genoa X uses AMD’s 3D chip-stacking technology, V-Cache, for additional on-chip memory. AMD is leveraging one of its latest families of EPYC server CPUs, code-named Genoa X, in-house to run the ...